1. Field of the Invention
The present invention relates to a counter circuit, and more specifically to a counter circuit having a ring counter and capable of freely and precisely adjusting a counted-down frequency generated by the ring counter.
2. Description of Related Art
One typical conventional counter circuit is composed of a ring counter and a programmable counter. In order to generate a desired frequency from a frequency of a given clock pulse (CP, count pulse), the program counter is programmed with a value obtained by dividing the frequency of the clock pulse by the desired frequency, and also by dividing an obtained quotient by a maximum count number of the ring counter, and deriving an integer component from a finally obtained quotient. For example assume that the clock pulse is of the frequency of 200 KHz and the desired frequency is 780 Hz, and also assume that the ring counter is composed of six stages so as to have the maximum counter number of "12". In this case, EQU COUNT NUMBER=(200 KHz+780 Hz).div.12.perspectiveto.21.36
Therefore, if the counter number of "21" is set to the program counter, EQU DESIRED FREQUENCY=1.div.{(1/200 KHz).times.21.times.12}.perspectiveto.794 Hz
Namely, an error is 1.8%
On the other hand, if the counter number of "22" is set to the program counter, EQU DESIRED FREQUENCY=1.div.{(1/200 KHz).times.22.times.12}.perspectiveto.758 Hz
Namely, an error is 2.8%
In this case, accordingly, the program counter is set with the counter number "21", so that the counter circuit is realized with the error of 1.8%.
As will be apparent from the above, the conventional counter circuit has been disadvantageous in that, since the ring counter constituting a polynomial counter has a fixed stage number (namely, bit number), when the frequency of the clock pulse (CP) is constant, an error from a desired frequency often becomes large.